1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a configuration of an electrostatic protection circuit.
2. Description of Related Art
There is a case that a semiconductor device is configured such that a plurality of circuits each having a different power source system for supplying a power source voltage is integrated in the identical chip. In such a case, typically, a plurality of power source pads to which the power source voltages are respectively supplied from the different power source systems and a plurality of ground pads which is arranged correspondingly to the plurality of power source pads, respectively, are arranged in the semiconductor device.
Also, the semiconductor device typically includes an electrostatic protection circuit for protecting an internal circuit from an ESD (electrostatic discharge) surge applied to an external pad. As mentioned above, in the semiconductor device in which the plurality of circuits each having the different power source voltage is integrated in the identical chip, an ESD protection element is connected between the power source pad and the ground pad in a pair of the power source pad and the ground pad. Thus, the internal circuit is protected from the ESD surge.
FIG. 1A is a circuit diagram showing an example of a typical configuration of the semiconductor device which includes a plurality of circuits each having a different power source system and electrostatic protection circuits for protecting the plurality of circuits. The semiconductor device in FIG. 1A includes a first power source pad 111, a first ground pad 112, a first power source line 113, a first ground line 114, an output circuit 115, a second power source pad 121, a second ground pad 122, a second power source line 123, a second ground line 124 and an input circuit 125. The output circuit 115 includes a PMOS transistor P3 and an NMOS transistor N3, as output transistors. The input circuit 125 includes a PMOS transistor P1 and an NMOS transistor N1. The output circuit 115 and the input circuit 125 configure an interface for transmitting a signal between circuits to which the power source voltages are supplied from the different power source systems, and are connected through a signal line 120.
When a usual operation is carried out, a first power source voltage VDD1 is supplied to the first power source pad 111, and a ground voltage is supplied to the first ground pad 112. The output circuit 115 and an internal circuit (not shown) connected thereto are operated at the first power source voltage VDD1. On the other hand, a second power source voltage VDD2 is supplied to the second power source pad 121, and the ground voltage is supplied to the second ground pad 122. The input circuit 125 and an internal circuit (not shown) connected thereto are operated at the second power source voltage VDD2.
ESD protection elements 116 and 126 and a protection diode pair D1 are arranged for the protection against the ESD surge. The ESD protection element 116 is connected between the first power source line 113 and the first ground line 114, and the ESD protection element 126 is connected between the second power source line 123 and the second ground line 124. The protection diode pair D1 is arranged between the first ground line 114 and the second ground line 124. At the time of the usual operation, the first ground line 114 and the second ground line 124 are electrically separated by the protection diode pair D1. When the ESD surge is applied to the first power source pad 111, the first ground pad 112, the second power source pad 121 and the second ground pad 122, the ESD protection elements 116 and 126 and the protection diode pair D1 serve as a route for discharging the ESD surge and consequently have a role for protecting the output circuit 115, the input circuit 125 and the other circuits.
The typical element used as the ESD protection elements 116 and 126 are off transistors. The off transistor implies a MOS transistor in which a potential of a gate is fixed such that the transistor is turned off at the time of the usual operation. Then, the ESD surge is discharged by a parasitic bipolar operation. Typically, when a NMOS transistor is used as the off transistor, a drain of the NMOS transistor is connected to the power source line, and a source and a gate of the NMOS transistor are connected to the ground line. On the other hand, when a PMOS transistor is used as the off transistor, a drain of the PMOS transistor is connected to the ground line, and a gate and a source of the PMOS transistor are connected to the power source line. In the off transistor, when the ESD surge is applied to its drain, the ESD surge is discharged by the parasitic bipolar operation. With the foregoing principle, the off transistor effectively functions as the ESD protection element.
In the circuit configuration shown in FIG. 1A, a breakdown mode noted by the inventor is a breakdown mode when the ESD surge is applied between the pads mutually belonging to the power source system. When an external circuit is not connected to the first power source pad 111, the first ground pad 112, the second power source pad 121 and the second ground pad 122 so that the power source voltage is not supplied, the gates of the PMOS transistor P3 and the NMOS transistor N3 are floating. Thus, there is a case that the PMOS transistor P3 or NMOS transistor N3 is turned on.
In such a situation, between the first power source pad 111 and the second ground pad 122, when the ESD surge with positive polarity relative to the second ground pad 122 as a reference is applied to the first power source pad 111 as shown in FIG. 1A, a stress voltage Vstress1 is applied between the gate and the source of the NMOS transistor N1 in the input circuit 125 through the first power source line 113, the PMOS transistor P3 and the signal line 120. This stress voltage Vstress1 is considerably high because the stress voltage Vstress1 becomes the sum of a clamp voltage VESD1 of the ESD protection element 116 and a clamp voltage VESD2 of the protection diode pair D1. Thus, there is a possibility that the NMOS transistor N1 is broken.
Also, as shown in FIG. 1B, between the first power source pad 111 and the second power source pad 121, when the ESD surge with positive polarity relative to the second power source pad 121 as a reference is applied to the first power source pad 111, the stress voltage Vstress1 is applied between the gate and the source of the NMOS transistor N1 and a stress voltage Vstress2 is applied between the gate and the source of the PMOS transistor P1 in the input circuit 125 through the first power source line 113, the PMOS transistor P3 and the signal line 120. At this time, the stress voltage Vstress1 applied to the NMOS transistor N1 becomes the sum of the clamp voltage VESD1 of the ESD protection element 116 and the clamp voltage VESD2 of the protection diode pair D1. Also, the stress voltage Vstress2 applied to the PMOS transistor P1 becomes the sum of the foregoing clamp voltages VESD1 and VESD2 and a clamp voltage VESD3 of the ESD protection element 126. Therefore, both of the stress voltages Vstress1 and Vstress2 are considerably high. Thus, there is a possibility that the NMOS transistor N1 and the PMOS transistor P1 are broken.
Moreover, the case that the ESD surge with positive polarity relative to the first power source pad 111 as a reference is applied to the second power source pad 121 between the second power source pad 121 and the first power source pad 111 and the case that the ESD surge with positive polarity relative to the first ground pad 112 as a reference is applied to the second power source pad 121 between the second power source pad 121 and the first ground pad 112 are also similar to the above described cases. When the ESD surge with positive polarity relative to the first power source pad 111 as a reference is applied to the second power source pad 121, the stress voltage Vstress1 applied to the NMOS transistor N1 becomes the sum of the clamp voltages VESD1 and VESD2. Also, the stress voltage Vstress2 applied to the PMOS transistor P1 becomes the sum of the clamp voltages VESD1, VESD2 and VESD3. Therefore, both of the stress voltages Vstress1 and Vstress2 are considerably high. Thus, there is a possibility that the NMOS transistor N1 and the PMOS transistor P1 are broken. In addition, when the ESD surge with positive polarity relative to the first ground pad 112 as a reference is applied to the second power source pad 121, the stress voltage Vstress2 applied to the PMOS transistor P1 becomes the sum of the clamp voltages VESD2 and VESD3, and there is a possibility that the PMOS transistor P1 is broken.
According to the consideration of the inventor, it is important to protect the NMOS transistor N1 and the PMOS transistor P1 from being broken by the foregoing breakdown mode.
In particular, when the off transistors are used as the ESD protection elements 116 and 126, the problem of the increase in the stress voltages Vstress1 and Vstress2 applied between the gates and the sources of the NMOS transistor N1 and the PMOS transistor P1, respectively, becomes severe. This is because in recent years, in association with advancements of miniaturization of MOS transistors, although a breakdown voltage VBD of a MOS transistor is decreased, an operational voltage (clamp voltage Vclamp) at which a parasitic bipolar operation is executed is not decreased. FIG. 2 is a graph showing a relation between a breakdown voltage VBD of a gate insulation film and a clamp voltage Vclamp when a NMOS transistor carries out a parasitic bipolar operation (a voltage while discharge caused by the parasitic bipolar operation is carried out). Although the breakdown voltage VBD is sharply decreased together with a reduction in a film thickness of the gate insulation film, the clamp voltage Vclamp is not decreased. This implies that in association with the advancements of the miniaturization of the MOS transistors, although the breakdown voltages VBD of the NMOS transistor N1 and the PMOS transistors P1 are decreased, the operational voltages at which the ESD protection elements 116 and 126 are operated are not decreased, which implies that a design window is made small.
As one method for solving the foregoing problem, a circuit configuration is known in which a thyristor is used as the ESD protection element and a trigger current is supplied by a triggering element operated at a low voltage (refer to a patent literature 1 and a non-patent literature 1). When a PMOS transistor that carries out a usual MOS operation to supply the trigger current is used as the triggering element, it is possible to decrease the operational voltage of the ESD protection element.    Patent Literature 1: Japanese Patent Publication No. JP-P 2008-218886A (corresponding to US Patent Publication No. US2008217650A1)    Non-Patent Literature 1: Y. Morishita et al., “A Low-Leakage SCR Design Using Trigger-PMOS Modulation for ESD Protection”, 2007 EOS/ESD Symposium Proceedings, 2007376.
However, the inventor has now discovered the following facts. According to the consideration of the inventor, the problem of the breakdown of the NMOS transistor N1 and the PMOS transistor P1 in the circuit configuration of FIGS. 1A and 1B cannot be solved only by decreasing the operational voltage of the ESD protection element. Specifically, in the circuit configurations of FIGS. 1A and 1B, when the ESD surge is applied, the stress voltage Vstress1 or Vstress2 is applied without change between the gate and the source of the NMOS transistor N1 or PMOS transistor P1 that is the element targeted for the protection. Thus, if the ESD protection elements 116 and 126 and the protection diode pair D1 do not function sufficiently, there is a possibility that the NMOS transistor N1 or PMOS transistor P1 is broken by applying the stress voltages Vstress1, Vstress2 between the source and the gate. The foregoing problem is not solved even if the ESD protection element having the above configuration, in which the PMOS transistor for carrying out the usual MOS operation is used to supply the trigger current to the thyristor, is used to reduce the operational voltage.